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Add unconditional branching.

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This commit is contained in:
cfreksen 2017-10-29 18:42:38 +01:00
parent 05782f6fca
commit a4885103c0
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GPG Key ID: EAC13EE101008978
1 changed files with 30 additions and 8 deletions
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38
stepper.py
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@ -51,6 +51,11 @@ def step(insns, terminator, blocks, stack_frames, ssa_env, global_env, memory,
def terminate(terminator, blocks, stack_frames, ssa_env, global_env, memory): def terminate(terminator, blocks, stack_frames, ssa_env, global_env, memory):
def clear_block_from_ssa_env(insns, ssa_env):
for (id, insn) in insns:
if id is not None and id in ssa_env:
del ssa_env[id]
if isinstance(terminator, ll.Ret): if isinstance(terminator, ll.Ret):
oper = terminator.oper oper = terminator.oper
if oper is None: if oper is None:
@ -64,6 +69,22 @@ def terminate(terminator, blocks, stack_frames, ssa_env, global_env, memory):
new_stack_frames = stack_frames[1:] new_stack_frames = stack_frames[1:]
return (new_insns, new_terminator, new_blocks, new_stack_frames, return (new_insns, new_terminator, new_blocks, new_stack_frames,
new_ssa_env, memory, oper_v) new_ssa_env, memory, oper_v)
elif isinstance(terminator, ll.Br):
label = terminator.label
next_block = blocks[label]
new_insns = next_block.insns
new_terminator = next_block.terminator
# TODO: Might need to find a better solution as we will ignore
# multiple assignments, if they are spread over multiple
# blocks.
clear_block_from_ssa_env(new_insns, ssa_env)
print('Jumping unconditionally to {}'
.format(label))
return (new_insns, new_terminator, blocks, stack_frames,
ssa_env, memory, None)
else: else:
err('Unknown LLVM terminator: {}' err('Unknown LLVM terminator: {}'
.format(terminator)) .format(terminator))
@ -118,18 +139,19 @@ def gogo():
data = r''' data = r'''
define i64 @tigermain (i64 %U_mainSL_8, i64 %U_mainDummy_9) { define i64 @tigermain (i64 %U_mainSL_8, i64 %U_mainDummy_9) {
%a = add i64 3, 5 ; please be 8 %a = add i64 3, 5 ; please be 8
br label %L1
L1:
%b = add i64 %a, %a %b = add i64 %a, %a
%c = add i64 %a, %b %c = add i64 %a, %b
%d = add i64 100, %c ret i64 %c
%e = mul i64 7, %b L2:
%f = sdiv i64 %e, 2 %d = add i64 %a, 1
%g = sub i64 %d, %f %e = add i64 10, %b
%h = or i64 1, %g ret i64 %e
%i = shl i64 %h, 2
ret i64 %g
} }
''' '''
print(data)
ast = p.parse(data) ast = p.parse(data)
tdecs = ast.tdecls tdecs = ast.tdecls