Add conditional branching.

This commit is contained in:
cfreksen 2017-10-29 19:28:19 +01:00
parent 344609e54b
commit 4aeb986d75
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GPG Key ID: EAC13EE101008978

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@ -12,6 +12,11 @@ def err(msg):
.format(msg)) .format(msg))
def warn(msg):
print('WARNING: {}'
.format(msg))
def step(insns, terminator, blocks, stack_frames, ssa_env, global_env, memory, def step(insns, terminator, blocks, stack_frames, ssa_env, global_env, memory,
tdecs, fdecs, call_res): tdecs, fdecs, call_res):
if len(insns) == 0: if len(insns) == 0:
@ -108,6 +113,30 @@ def terminate(terminator, blocks, stack_frames, ssa_env, global_env, memory):
print('Jumping unconditionally to {}' print('Jumping unconditionally to {}'
.format(label)) .format(label))
return (new_insns, new_terminator, blocks, stack_frames,
ssa_env, memory, None)
elif isinstance(terminator, ll.Cbr):
ty = terminator.ty
if ty != ll.SimpleType.I1:
warn('Branching based on value of type {}. You ought to branch on {}'
.format(ll.ty2s(ty), ll.ty2s(ll.SimpleType.I1)))
operand = terminator.oper
operand_v = eval_oper(operand, ssa_env, global_env)
if operand_v:
label = terminator.then_label
else:
label = terminator.else_label
next_block = blocks[label]
new_insns = next_block.insns
new_terminator = next_block.terminator
clear_block_from_ssa_env(new_insns, ssa_env)
# TODO
print('Operand was {}. Branching to {}'
.format(operand_v, label))
return (new_insns, new_terminator, blocks, stack_frames, return (new_insns, new_terminator, blocks, stack_frames,
ssa_env, memory, None) ssa_env, memory, None)
else: else:
@ -182,14 +211,14 @@ def gogo():
data = r''' data = r'''
define i64 @tigermain (i64 %U_mainSL_8, i64 %U_mainDummy_9) { define i64 @tigermain (i64 %U_mainSL_8, i64 %U_mainDummy_9) {
%a = add i64 3, 5 ; please be 8 %a = add i64 3, 5 ; please be 8
br label %L1 %c = icmp eq i64 %a, 9
br i1 %c, label %L1, label %L2
L1: L1:
%b = add i64 %a, %a %b = add i64 %a, %a
%c = icmp eq i64 %a, %b
ret i1 %c ret i1 %c
L2: L2:
%d = add i64 %a, 1 %d = add i64 %a, 1
%e = add i64 10, %b %e = add i64 10, %d
ret i64 %e ret i64 %e
} }
''' '''